NoC-MRAM architecture for memory-based computing: Database-search case study

The paper presents a novel flexible low-power architecture for memory-based computing that relies on a NoC and power-gated distributed MRAM. The proposed approach is demonstrated with a database search application implemented with a Sparse-Neural-Network (SNN). Multiple SystemC simulations have been conducted over the MRAM-based computing architecture targeting hundreds of database queries. The results show hit rates of about 95%, impressive power gains compared to SRAM, and significant impact of power-gating. The results also provide an evidence on the feasibility of using power-gated MRAM associated with a NoC as a solution for low power implementation of memory-based computing.

[1]  H. Ohno,et al.  A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme , 2013, IEEE Journal of Solid-State Circuits.

[2]  Giovanni De Micheli,et al.  The Programmable Logic-in-Memory (PLiM) computer , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[3]  Chein-Wei Jen,et al.  On the design automation of the memory-based VLSI architectures for FIR filters , 1993 .

[4]  S. Bhunia,et al.  A Scalable Memory-Based Reconfigurable Computing Framework for Nanoscale Crossbar , 2012, IEEE Transactions on Nanotechnology.

[5]  Vincent Gripon,et al.  A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture , 2014, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[6]  Jason Cong,et al.  Invited: Heterogeneous datacenters: Options and opportunities , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[7]  Kiyoung Choi,et al.  Active Memory Processor for Network-on-Chip-Based Architecture , 2012, IEEE Transactions on Computers.

[8]  Luca Benini,et al.  Energy-efficient GPGPU architectures via collaborative compilation and memristive memory-based computing , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[9]  Vincent Gripon,et al.  Sparse Neural Networks With Large Learning Diversity , 2011, IEEE Transactions on Neural Networks.

[10]  Swarup Bhunia,et al.  Memory-based computing for performance and energy improvement in multicore architectures , 2012, GLSVLSI '12.

[11]  Martha Johanna Sepúlveda,et al.  Notifying memories: A case-study on data-flow applications with NoC interfaces implementation , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[12]  Andrew S. Cassidy,et al.  A million spiking-neuron integrated circuit with a scalable communication network and interface , 2014, Science.

[13]  Martha Johanna Sepúlveda,et al.  Scalable NoC-based architecture of neural coding for new efficient associative memories , 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[14]  E. Culurciello,et al.  NeuFlow: Dataflow vision processing system-on-a-chip , 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).