A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump

Power consumption has become a critical design criterion for integrated circuits given the growing importance of portable battery-operated devices. A typical CMOS gate driven by power supply (VDD), draws energy equal to CLVDD 2 during every cycle of operation. We propose a new approach to recycle the charge with an adiabatic charge pump that moves the slower adiabatic components away from the critical path of logic. The critical path of the system, and hence the delay, do not change. This is achieved by overlapping the adiabatic charge pump delays with the computing path logic delays. Many embedded high performance applications such as digital signal processing (DSP), which exhibit datapath parallelism, are ideal candidates for this scheme. The proposed method has been implemented in DSP computations. SPICE simulations-based results indicate that the proposed scheme reduces energy consumption in these DSP circuits by as much as 18% (on average 9.94%) with no perceptible loss in performance. The area penalty for these energy savings are in the 1%-2% range, The leakage energy reduction in 45-nm BPTM averages 46%.

[1]  A. Guyot,et al.  Low power CMOS digital design , 1998, Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186).

[2]  Todd M. Austin,et al.  The SimpleScalar tool set, version 2.0 , 1997, CARN.

[3]  Leon O. Chua,et al.  Topological generation and analysis of voltage multiplier circuits , 1977 .

[4]  Kaushik Roy,et al.  Low-Power CMOS VLSI Circuit Design , 2000 .

[5]  Jean-Luc Danger,et al.  Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[6]  Jan M. Rabaey,et al.  Digital Integrated Circuits , 2003 .

[7]  D. H. Horrocks,et al.  Overview and design directions for low-power circuits and architectures for digital signal processing , 1995 .

[8]  Nestoras Tzartzanis,et al.  Low-power digital systems based on adiabatic-switching principles , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[9]  William C. Athas,et al.  An energy-efficient CMOS line driver using adiabatic switching , 1994, Proceedings of 4th Great Lakes Symposium on VLSI.

[10]  Yu Cao,et al.  New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[11]  Uming Ko,et al.  Low-power design techniques for high-performance CMOS adders , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[12]  John F. Dickson,et al.  On-Chip High-Voltage Generation in Integrated Circuits Using an Improved Multiplier Technique , 1976 .

[13]  Tughrul Arslan,et al.  Algorithmic low power FIR cores , 2003 .

[14]  L. Pylarinos,et al.  Charge Pumps: An Overview , 2003 .

[15]  L. J. Svensson,et al.  Driving a capacitive load without dissipating fCV/sup 2/ , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[16]  Martin Fischer,et al.  Fully integrated passive UHF RFID transponder IC with 16.7-μW minimum RF input power , 2003, IEEE J. Solid State Circuits.

[17]  Kaushik Roy,et al.  Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[18]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について － , 2004 .

[19]  Norman P. Jouppi,et al.  WRL Research Report 93/5: An Enhanced Access and Cycle Time Model for On-chip Caches , 1994 .