Performance improvements in multi-gigabit/s oversampling ADCs

Design of a complete multi-GHz GaAs HEMT sigma-delta ADC is presented. A novel process insensitive technique has been applied to the design of the /spl Sigma//spl Delta/ modulator and new GaAs source-follower DCFL (SDCFL) complex gates were used in the comb decimator. Simulation results of the modulator confirm that the SNR at the modulator output is relatively insensitive to variations in process parameters. Measurements on high-speed adder test circuits indicate that a speed of 2 GHz with 2.2 W power dissipation can be obtained from the decimator.