Programmable logic arrays in single-electron transistor technology

This paper presents a programmable logic array (PLA) layered structure composed of single-electron tunneling transistor (SET) devices. In this array bits of information are represented by the presence or absence of single electrons at conducting islands. A layer in the array is composed of a SET summing-inverter cell replicated for performing a programmable Boolean operation of its inputs. A number of layers are added on to implement the logic function. We confirm the correct and stable operation of the PLA matrix using a well-known single-electron circuit simulator based on Monte Carlo technique. We then discuss challenges facing SETs and end with conclusions.