Scan Test Data Volume Reduction for SoC Designs in EDT Environment

This paper presents approaches to reduce scan test data volume for SoC designs in EDT environment. They target different factors impacting scan test data volume - scan channel count, pattern count and shift cycles. In the experiments on an industrial SoC design, up to 23% scan test data volume can be reduced.

[1]  Brion L. Keller,et al.  OPMISR: the foundation for compressed ATPG vectors , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[2]  Erik Jan Marinissen,et al.  On using rectangle packing for SOC wrapper/TAM co-optimization , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[3]  Peter Wohl,et al.  Increasing Scan Compression by Using X-chains , 2008, 2008 IEEE International Test Conference.

[4]  Nilanjan Mukherjee,et al.  Embedded deterministic test , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Sudhakar M. Reddy,et al.  On Concurrent Test of Core-Based SOC Design , 2002, J. Electron. Test..