Implementation of high speed vedic multiplier using modified adder

Multipliers are the most important block in any arithmetic and logic unit, accumulators and Digital signal processors. Due to the increasing constraints on delay, design of faster multipliers is emphasized. Among several multipliers, Vedic multipliers are preferred for their speed of operation. Among the sixteen sutras in Vedic multiplication techniques our proposed “URDHVA TIRYAKBHYAM” a most efficient technique in-terms of speed. In this project we aim at developing a multiplier using modified Adder which implements the “URDHVA TIRYAKBHYAM” sutra with improved speed of operation. Adders are vastly implemented in the critical path of many blocks of microprocessor chips. Our proposed adder is not only used for arithmetic logic units (ALUs). This adders are used in other parts of processor where they are used to calculate indices of table, corresponding condition and addresses. The efficiency of the digital system is greatly influenced by the performance of these adders. In this paper we proposed new innovative modified carry select adder with performance improvement in delay and area used. The most important parameters to be noted to measure the performance of adder designs are computation time and area. To compare results we have simulated types of adders in existing by using Xilinx tool and the results are compared.