A 0.13-$\mu$ m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

A 6 Gb/s/pin transceiver for DRAM interfaces is implemented in a 0.13-mum CMOS process. Pseudo-differential signaling to overcome problems of conventional single-ended signaling is proposed. In a conventional single-ended signaling, the reference signal from a transmitter is generally used to reduce the common-mode noise which is induced by simultaneous switching noise (SSN). However, as supply voltage becomes low and data rate increases, the reference signal reduces the voltage and timing margin of receiver inputs. The proposed transceiver uses the pseudo-differential signaling without the reference signal and encoding schemes using the relation between neighboring data are proposed to remove the reference signal. In the receiver, transition-check circuit (TCC) is used to convert encoded data into original data before encoding. The proposed pseudo-differential signaling increases the eye-opening of 1:2 demuxed outputs of the receiver by 65 ps. The transceiver dissipates 242.5 mW and its active area is 1.0 mm times 0.3 mm.

[1]  Stefanos Sidiropoulos,et al.  A semidigital dual delay-locked loop , 1997 .

[2]  Karthik Gopalakrishnan,et al.  Single-ended transceiver design techniques for 5.33Gb/s graphics applications , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[3]  K. Gotoh,et al.  A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11- $\mu{\hbox {m}}$ CMOS , 2007, IEEE Journal of Solid-State Circuits.

[4]  A. Hajimiri,et al.  Cancellation of crosstalk-induced jitter , 2006, IEEE Journal of Solid-State Circuits.

[5]  A. Sedra.  Microelectronic circuits , 1982 .

[6]  A. Hajimiri,et al.  Phase and amplitude pre-emphasis techniques for low-power serial links , 2006, IEEE Journal of Solid-State Circuits.

[7]  Woo-Jin Lee,et al.  An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion , 2008, IEEE Journal of Solid-State Circuits.

[8]  이재승,et al.  A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration , 2008 .

[9]  Young-Hyun Jun,et al.  A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[10]  J. Lee,et al.  A 40 Gb/s clock and data recovery circuit in 0.18 /spl mu/m CMOS technology , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[11]  B. Razavi,et al.  A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector , 2001, IEEE J. Solid State Circuits.

[12]  William J. Dally,et al.  Digital systems engineering , 1998 .

[13]  Won Namgoong,et al.  Multilevel differential encoding with precentering for high-speed parallel link transceiver , 2005, IEEE Journal of Solid-State Circuits.

[14]  K. Nishimura,et al.  A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS , 2006, IEEE Journal of Solid-State Circuits.

[15]  Won Namgoong,et al.  High-Speed Single-Ended Parallel Link Based on Three-Level Differential Encoding , 2009, IEEE Journal of Solid-State Circuits.

[16]  Behzad Razavi,et al.  A 40 Gb/s clock and data recovery circuit in 0.18 μm CMOS technology , 2003 .

[17]  Shyh-Jye Jou,et al.  Low switching noise and load-adaptive output buffer design techniques , 2001 .

[18]  Lee-Sup Kim,et al.  A 500MHz DLL with second order duty cycle corrector for low jitter , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[19]  Peter Gregorius,et al.  A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques , 2010, IEEE Journal of Solid-State Circuits.

[20]  Ting Wu,et al.  Clocking circuits for a 16Gb/s memory interface , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[21]  Ting Wu,et al.  A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface , 2009, IEEE Journal of Solid-State Circuits.

[22]  Tao Wang,et al.  A new current-mode incremental signaling scheme with applications to Gb/s parallel links , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[23]  Lee-Sup Kim,et al.  A 3.2-Gb/s transceiver with a quarter-rate linear phase detector reducing the phase offset , 2008, 2008 IEEE Asian Solid-State Circuits Conference.

[24]  Jae-Hyung Lee,et al.  A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[25]  Anthony Chan Carusone,et al.  Differential signaling with a reduced number of signal paths , 2001 .