A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS

This paper presents a fully differential transimpedance amplifier (TIA) realized in a standard 65-nm CMOS process, where a novel mirrored-cascode (MC) input configuration is proposed for differential signaling, i.e., an NMOS cascode amplifier with a resistive feedback for negative output and its MC amplifier via an ac-coupling capacitor for positive output. For bandwidth extension, the third-order asymmetric transformers were carefully employed. Measured results of the proposed MC differential (MCD) TIA demonstrate 54-dB<inline-formula> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> transimpedance gain, 40-GHz bandwidth for 50-fF photodiode capacitance, <inline-formula> <tex-math notation="LaTeX">$19.8-\text{pA}/\sqrt {\mathrm {Hz}}$ </tex-math></inline-formula> average noise current spectral density, ±10-ps group delay variation, and 55.2-mW power consumption. Eye diagrams for 32 Gb/s 2<sup>15</sup> –1 pseudo random binary sequence (PRBS) were measured with the input currents of 100–1.5 mApp. The chip occupies the area of 0.6 mm<sup>2</sup> including I/O pads.

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