Self-termination scheme for high-speed chip-to-chip data communication

In this work we propose self-termination scheme for high-speed current-mode differential signaling. This scheme eliminates the need of any dedicated passive terminator avoiding signal reflection both at the transmitter and receiver. We present fully differential, high speed transmitter/receiver(Tx/Rx) pair suitable for this self-terminated differential current-mode signaling scheme. We propose high-speed, power efficient self terminating transmitter with modified Cherry-Hooper topology. Also propose, self terminated, differential current-mode receiver realized by modified regulated gate cascode (RGC) based common-source (CS) trans-impedance amplifier (TIA) with folded active inductor peaking. The transmitter and receiver circuits are implemented in 1.8-V, 0.18-µm Digital CMOS technology with an ƒT of 27-GHz. The designed transmitter and receiver circuits, handle data rates up-to 8-Gb/s for the targeted BER of 10−12, while transmitting the data over backplane FR4 PCB trace of length 7.5-inch. The power consumed in the transmitter and receiver circuits is 10.31-mW and 10.17-mW respectively at 8-Gb/s data rate.

[1]  Mark Horowitz,et al.  High-speed electrical signaling: overview and limitations , 1998, IEEE Micro.

[2]  Behzad Razavi.  Design of intergrated circuits for optical communications , 2002 .

[3]  Hans-Martin Rein,et al.  Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s , 1996, IEEE J. Solid State Circuits.

[4]  Shen-Iuan Liu,et al.  A 1V 4.2mW fully integrated 2.5Gb/s CMOS limiting amplifier using folded active inductors , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[5]  Xin Wang,et al.  15.1 OC-192 Transmitter in Standard 0.18µm CMOS , 2002 .

[6]  T.S. Kalkur,et al.  High-speed current-mode logic amplifier using positive feedback and feed-forward source-follower techniques for high-speed CMOS I/O buffer , 2005, IEEE Journal of Solid-State Circuits.

[7]  E. M. Cherry,et al.  The Design of Wide-Band Transistor Feedback Amplifiers , 1963 .

[8]  Michael P. Flynn,et al.  A low-power 8-PAM serial-transceiver in 0.5 μm digital CMOS , 2001 .

[9]  T. Lee,et al.  A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver , 2000, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[10]  W. Guggenbuhl,et al.  A high-swing, high-impedance MOS cascode circuit , 1990 .

[11]  Xin Wang,et al.  OC-192 transmitter in standard 0.18 /spl mu/m CMOS , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[12]  T. J. Gabara,et al.  Digitally adjustable resistors in CMOS for high-performance applications , 1992 .