0.3 μm BiCMOS SRAM technologies with 1.5V operation

This paper describes the process integration technologies for low-voltage BiCMOS SRAM operation, including a low collector resistance process for high-speed boost-BiNMOS peripheral circuits, a symmetrical cell layout design with a triple-well structure and an optimized gate oxide thickness for a word-line boosting during write and read cycles. These technologies were successfully implemented using 0.3 μm BiCMOS devices where an address access time of 6ns and a high soft-error immunity were demonstrated at 1.5 V for a 4 Mb BiCMOS SRAM.