Automated High-level Verification Against Clocked Algorithmic Specifications

Abstract We present a new method for automated verification of a circuit against an algorithmic specification where clock statements are used to indicate the scheduling of operations. We use a representation of the circuit and its specification where each data path register is treated as a unit, as in high-level synthesis. Therefore, in contrast with BDD-based methods, the time it takes to verify a circuit is independent of the width of the data path. We have been able to verify the Tamarack-3 microprocessor without any user guidance in 34 seconds, including parsing and compilation, on an IBM RS/6000 workstation.