Automated High-level Verification Against Clocked Algorithmic Specifications
暂无分享,去创建一个
[1] Alice C. Parker,et al. The high-level synthesis of digital systems , 1990, Proc. IEEE.
[2] Robert K. Brayton,et al. Implicit state enumeration of finite state machines using BDD's , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[3] Francisco Corella. Automated Verification of Behavioral Equivalence for Microprocessors , 1994, IEEE Trans. Computers.
[4] Reinaldo A. Bergamaschi,et al. Verification of Synchronous Sequential Circuits Obtained from Algorithmic Specifications , 1991 .
[5] Olivier Coudert,et al. A unified framework for the formal verification of sequential circuits , 1990, ICCAD 1990.
[6] Edmund M. Clarke,et al. Sequential circuit verification using symbolic model checking , 1991, DAC '90.
[7] Thomas Filkorn. A Method for Symbolic Verification of Synchronous Circuits , 1991 .