Limit parameters: the general solution of the worst-case problem for the linearized case (IC design)

The use of limit parameters to determine the manufacturability of an IC design is addressed. On the basis of a sensitivity analysis of the circuit, a realistic worst-case (e.g. 3 sigma ) is estimated. For this value, limit-parameter sets are calculated for every objective. These parameter sets include correct variances and correlations for the transistor parameters, which are derived from measurements in the fabrication process. Since the method is based on a sensitivity analysis, the enormous effort of a Monte Carlo method can be avoided.<<ETX>>

[1]  M. J. B. Bolt,et al.  A Novel Approach to Realistic Worst-case Simulations of CMOS Circuits , 1989, ESSDERC '89: 19th European Solid State Device Research Conference.

[2]  James Robertson,et al.  Realistic worst-case parameters for circuit simulation , 1987 .

[3]  K. Antreich,et al.  Design centering by yield prediction , 1982 .

[4]  Lars Taxén,et al.  Stochastic optimization in system design , 1981 .

[5]  M. A. Styblinski,et al.  Algorithms and Software Tools for IC Yield Optimization Based on Fundamental Fabrication Parameters , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  B. Baylac,et al.  ``WCAP'' : Worst Case Analysis Program : A Tool for Statistical Circuit Simulation , 1988, ESSDERC '88: 18th European Solid State Device Research Conference.

[7]  Sani R. Nassif,et al.  A Methodology for Worst-Case Analysis of Integrated Circuits , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Stephen W. Director,et al.  Statistical circuit design : a somewhat biased survey , 1981 .

[9]  Ping Yang,et al.  Parametric yield optimization for MOS circuit blocks , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  A. R. Alvarez,et al.  A methodology for worst-case design of BiCMOS integrated circuits , 1988, Proceedings of the 1988 Bipolar Circuits and Technology Meeting,.

[11]  John J. Barnes,et al.  Statistical Circuit Simulation Modeling of CMOS VLSI , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Sung-Mo Kang,et al.  Statistical Performance Modeling and Parametric Yield Estimation of MOS VLSI , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.