论文信息 - Hardware Implementation of Instruction Level Parallel Architecture Incorporating Special Functional Units for Image Processing Algorithms - 字舞流文

Hardware Implementation of Instruction Level Parallel Architecture Incorporating Special Functional Units for Image Processing Algorithms

. S.K.Srivatsa | . M.Kannan

[1] Kattamuri Ekanadham,et al. Incorporating Data Flow Ideas into von Neumann Processors for Parallel Execution , 1987, IEEE Transactions on Computers.

[2] Kemal Ebcioglu,et al. Compilers for Instruction-Level Parallelism , 1997, Computer.

[3] Mateo Valero,et al. Exploiting instruction- and data-level parallelism , 1997, IEEE Micro.

[4] David J. Lilja. Exploiting the parallelism available in loops , 1994, Computer.

[5] Gurindar S. Sohi,et al. Instruction Issue Logic for High-Performance Interruptible, Multiple Functional Unit, Pipelines Computers , 1990, IEEE Trans. Computers.