Coupled analysis of electromigration reliability and performance in ULSI signal nets

In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. This paper presents for the first time a rigorous coupled analysis of AC electromigration that are prevalent in signal lines and thermal effects arising due to Joule heating of the wires. The analysis is applied to study the effect of technology scaling using ITRS data, wherein the effects of increasing interconnect (Cu) resistivity with line dimensions and the effect of a finite barrier metal thickness have been included. Finally, we have also quantified the reliability implications for minimum sized vias in optimally buffered signal nets. Our analysis suggests that for the optimally buffered interconnects, while the maximum current density in the line remains limited by the performance, the current density in the vias exceeds the reliability limits and therefore requires careful consideration in the physical design process flow.

[1]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[2]  Alberto L. Sangiovanni-Vincentelli,et al.  On thermal effects in deep sub-micron VLSI interconnects , 1999, DAC '99.

[3]  Chenming Hu,et al.  Characterization of self-heating in advanced VLSI interconnect lines based on thermal finite element simulation , 1998 .

[4]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[5]  Kaustav Banerjee,et al.  Investigation of self-heating phenomenon in small geometry vias using scanning Joule expansion microscopy , 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).

[6]  D. Gardner,et al.  Influence of line dimensions on the resistance of Cu interconnections , 1998, IEEE Electron Device Letters.

[7]  Kaustav Banerjee,et al.  Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[8]  W. Hunter.  Self-consistent solutions for allowed interconnect current density. II. Application to design guidelines , 1997 .

[9]  Kaustav Banerjee,et al.  Quantitative projections of reliability and performance for low-k/Cu interconnect systems , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

[10]  J. C. Anderson,et al.  The use of thin films in physical investigations : a NATO Advanced Study Institute held at the Imperial College of Science and Technology , University of London, July 19-24 1965 , 1966 .

[11]  E. Jordan,et al.  Electromagnetic Waves and Radiating Systems , 1951 .

[12]  W. Dally.  Interconnect-limited VLSI architecture , 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

[13]  Rolf E. Hummel,et al.  Electromigration in integrated circuits , 1997 .

[14]  R. W. Vook,et al.  In-situ ultra-high vacuum studies of electromigration in copper films , 1995 .

[15]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[16]  Robert K. Brayton,et al.  Planning for performance , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[17]  Kimiaki Shimokawa,et al.  Reduction of wiring capacitance with new low dielectric SiOF interlayer film for high speed/low power sub-half micron CMOS , 1994, Proceedings of 1994 VLSI Technology Symposium.

[18]  Chenming Hu,et al.  Projecting interconnect electromigration lifetime for arbitrary current waveforms , 1990 .

[19]  A. Amerasekera,et al.  The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal , 1996, International Electron Devices Meeting. Technical Digest.

[20]  J. Black,et al.  Electromigration—A brief survey and some recent results , 1969 .

[21]  Robert Rosenberg,et al.  Electromigration path in Cu thin-film lines , 1999 .

[22]  Syed A. Rizvi.  Analyzing the tolerance and controls on critical dimensions and overlays as prescribed by the National Technology Roadmap for Semiconductors , 1997, Other Conferences.

[23]  Frank Cano,et al.  A practical approach to static signal electromigration analysis , 1998, DAC.

[24]  Jiang Tao,et al.  Modeling and characterization of electromigration failures under bidirectional current stress , 1996 .

[25]  W. Hunter.  Self-consistent solutions for allowed interconnect current density. I. Implications for technology evolution , 1997 .

[26]  Sung-Mo Kang,et al.  Interconnect thermal modeling for accurate simulation of circuittiming and reliability , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[27]  M. Bohr.  Interconnect scaling-the real limiter to high performance ULSI , 1995, Proceedings of International Electron Devices Meeting.

[28]  J. Black.  Electromigration failure modes in aluminum metallization for semiconductor devices , 1969 .