Analytical Modeling and Simulation for Dual Metal Gate Stack Architecture (DMGSA) Cylindrical/Surrounded Gate MOSFET
暂无分享,去创建一个
[1] J. Plummer,et al. Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's , 1997, IEEE Electron Device Letters.
[2] Fumio Horiguchi,et al. Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's , 1991 .
[3] R. Degraeve,et al. Reliability Comparison of Triple-Gate Versus Planar SOI FETs , 2006, IEEE Transactions on Electron Devices.
[4] Subhasis Haldar,et al. Impact of graded channel (GC) design in fully depleted cylindrical/surrounding gate MOSFET (FD CGT/SGT) for improved short channel immunity and hot carrier reliability , 2007 .
[5] Subhasis Haldar,et al. An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET , 2012, Microelectron. J..
[6] K. Itoh,et al. Simulation of sub-0.1- mu m MOSFETs with completely suppressed short-channel effect , 1993, IEEE Electron Device Letters.
[7] K. K. Young. Short-channel effect in fully depleted SOI MOSFETs , 1989 .
[8] Morteza Fathipour,et al. The influence of the stacked and double material gate structures on the short channel effects in SOI MOSFETs , 2004, Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004..
[9] Fumio Horiguchi,et al. Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits , 1991 .
[10] Kaushik Roy,et al. Double-gate SOI devices for low-power and high-performance applications , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[11] Emmanuel Dubois,et al. Short-channel effect immunity and current capability of sub-0.1-micron MOSFET's using a recessed channel , 1996 .
[12] J.M.C. Stork,et al. The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs , 1999 .
[13] Jong-Tea Park,et al. Pi-Gate SOI MOSFET , 2001, IEEE Electron Device Letters.
[14] Abhinav Kranti,et al. An accurate 2D analytical model for short channel thin film fully depleted cylindrical/surrounding gate (CGT/SGT) MOSFET , 2001 .
[15] Y. Naveh,et al. Modeling of 10-nm-scale ballistic MOSFET's , 2000, IEEE Electron Device Letters.
[16] Chenming Hu,et al. Dual work function metal gate CMOS technology using metal interdiffusion , 2001, IEEE Electron Device Letters.
[17] Subhasis Haldar,et al. Modeling and simulation of asymmetric gate stack (ASYMGAS)-MOSFET , 2003 .
[18] Ken K. Chin,et al. Dual-material gate (DMG) field effect transistor , 1999 .
[19] Fumio Horiguchi,et al. A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's , 1995 .
[20] Jae Bin Lee,et al. An Analytical Model for Deriving the 3-D Potentials and the Front and Back Gate Threshold Voltages of a Mesa- Isolated Small Geometry Fully Depleted SOI MOSFET , 2012 .
[21] T.-J.K. Liu,et al. Three-Dimensional FinFET Source/Drain and Contact Design Optimization Study , 2009, IEEE Transactions on Electron Devices.
[22] Jason C. S. Woo,et al. Gate Stack Architecture Analysis and Channel Engineering in Deep Sub-Micron MOSFETs , 1999 .
[23] R. S. Gupta,et al. Assessment of Ambipolar Behavior of a Tunnel FET and Influence of Structural Modifications , 2012 .
[24] Jong-Ho Lee,et al. A 40 nm body-tied FinFET (OMEGA MOSFET) using bulk Si wafer , 2003 .