A Co-Verification Tool for a High Level Language Compiler for FPGAs

The authors have described a method of testing various implementations of co-designs generated by the SA-C compiler. Each form can be examined using co-simulation. The host code is able to communicate with a FPGA board simulated in ModelSim as if it were physical hardware. The co-simulation approach briefly described in this paper allows us to test and analyze all parts of the complete co-design. In essence, the compiler is able to perform automated co-verification for any SA-C program. At the highest level of simulation, it allows functional verification of the VHDL generated by the compiler. At the lowest level of detail, the FPGA simulation is phase accurate and mimics the hardware behavior down to the individual configurable logic block