Fast and accurate cycle estimation through hybrid instruction set simulation for embedded systems

Execution time analysis is essential during the design of real-time embedded systems to verify all timing requirements are met. With rapid increase in complexity of modern hardware components, it becomes much more difficult to develop an accurate timing model for a target hardware, which serves as a basis for static timing analysis. Recently, simulation-based dynamic timing analysis techniques are becoming an attractive solution to predict the execution time of software in a fast and accurate manner. However, most of existing simulation-based timing analysis techniques are limited to simulate the temporal behavior of a processor without consideration of other peripheral devices such as storage and network, leading to less accuracy. In this paper, we propose an accurate cycle estimation framework which allows to use multiple instruction set simulators to simulate not only processors but also diverse peripheral devices. An instruction set simulator runs on a host machine to mimic functional behaviors of instructions running on a target hardware. It allows to estimate the execution time of software in a fast and accurate way and validate a system even when its target hardware does not yet exist or is not available.