A Segmented Data-Weighted-Averaging Technique
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[1] R. Baird,et al. Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging , 1995 .
[2] I. Fujimori,et al. A 90 dB SNR, 2.5 MHz output rate ADC using cascaded multibit /spl Delta//spl Sigma/ modulation at 8x oversampling ratio , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
[3] W. Sansen,et al. A high-performance multibit /spl Delta//spl Sigma/ CMOS ADC , 2000, IEEE Journal of Solid-State Circuits.
[4] L. Longo,et al. A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8/spl times/ oversampling ratio , 2000, IEEE Journal of Solid-State Circuits.
[5] Gabor C. Temes,et al. Split-set data weighted averaging , 2006 .
[6] Feng Chen,et al. A High Resolution Multibit Sigma-delta Modulator With Individual Level Averaging , 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.