Synchronous memory device with narrow data skew

1. Technical Field of the invention defined in the claims It relates to a synchronous semiconductor memory device having a narrow data skew. 2. The invention attempts to solve the technical challenges The invention improves the wave pipelined to propagate data in a row to provide a semiconductor memory device to increase the operation maahjin internal signal. 3. Resolution of the subject matter of the invention, It is controlled with the external clock from the system by an address to the input address buffer, the column predecoder, the column selection gate, input and output sense amplifier, a data bus, a semiconductor formed of a wave pipeline type, including the data lead path to the data output buffer in the memory device, are connected to any one of the rear end on the data path, at least one latch circuit for removing data skew in synchronization from the external clock at the moment in which the data lead command is given moment or another column address has been determined, that is provided as a base. 4. An important use of the invention, The invention is preferably used in a semiconductor memory device.