A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme

This paper describes three circuit technologies indispensable for high-bandwidth multibank DRAM's. (1) A clock generator based on a bidirectional delay (BDD) eliminates the output skew. The BDD measures the cycle time as the quantity charged or discharged of an analog quantity, and replicates it in the next cycle. This achieves a 0.18-mm/sup 2/, two-cycle-lock clock generator operating from 25 to 167 MHz with a 30-ps resolution. (2) A quad-coupled receiver eliminates the internal skew caused by the difference between a rise input and a fall input by 40%. (3) An interbank shared redundancy scheme (ISR) with a variable unit redundancy (VUR) efficiently increases yield in multibank DRAM's. The ISR allows redundancy match circuits to be shared with two or more banks. The VUR allows the number of units replaced to be variable. These circuit technologies achieved a 250-Mb/s/pin, 8-bank, 1-Gb double-data-rate synchronous DRAM.

[1]  Y. Serizawa,et al.  A 1 Gb SDRAM with ground level precharged bitline and non-boosted 2.1 V word line , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[2]  H. Aoki,et al.  An on-chip timing adjuster with sub-100-ps resolution for a high-speed DRAM interface , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[3]  John K. DeBrosse,et al.  Fault-tolerant designs for 256 Mb DRAM , 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

[4]  S. Nakazawa,et al.  256 Mbit synchronous DRAM , 1997 .

[5]  David A. Johns,et al.  Analog Integrated Circuit Design , 1996 .

[6]  Martin Gall,et al.  A 220-mm/sup 2/, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture , 1998 .

[7]  Yoshinori Okajima,et al.  Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface (Special Issue on ULSI Memory Technology) , 1996 .

[8]  Y. Takai,et al.  A 250 Mb/s 1 Gb double data rate SDRAM with a bi-directional delay and an inter-bank shared redundancy scheme , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[9]  Richard B. Watson,et al.  Clock Buffer Chip With Absolute Delay Regulation Over Process And Environmental Variations , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[10]  Chi-Chang Wang,et al.  A 3.3-V/5-V low power TTL-to-CMOS input buffer , 1998 .

[11]  Seung-Moon Yoo,et al.  A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth , 1996, IEEE J. Solid State Circuits.

[12]  Masashi Horiguchi,et al.  A flexible redundancy technique for high-density DRAMs , 1991 .

[13]  T. Matano,et al.  A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[14]  Shimizu,et al.  A 10ps Jitter 2 Clock Cycle Lock Time Cmos Digital Clock Generator Based On An Interleaved Synchronous Mirror Delay Scheme , 1997, Symposium 1997 on VLSI Circuits.