GECO: A Tool for Automatic Generation of Error Control Codes for Computer Applications
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[1] Shigeo Kaneda,et al. A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications , 1984, IEEE Transactions on Computers.
[2] Larry A. Dunning. SEC-BED-DED Codes for Error Control in Byte-Organized Memory Systems , 1985, IEEE Transactions on Computers.
[3] Larry A. Dunning,et al. Code Constructions for Error Control in Byte Organized Memory Systems , 1983, IEEE Transactions on Computers.
[4] Cristina Silvano,et al. VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes , 1995, Proceedings of the 8th International Conference on VLSI Design.
[5] Chin-Long Chen,et al. Measurement and Generation of Error Correcting Codes for Package Failures , 1978, IEEE Transactions on Computers.
[6] M. Y. Hsiao,et al. A class of optimal minimum odd-weight-column SEC-DED codes , 1970 .
[7] Toshio Yamada,et al. A 4-Mbit DRAM with 16-bit concurrent ECC , 1988 .
[8] J. O. Nicholson. The RISC system/6000 SMP system , 1995, Digest of Papers. COMPCON'95. Technologies for the Information Superhighway.
[9] Shu Lin,et al. Error control coding : fundamentals and applications , 1983 .
[10] Chin-Long Chen,et al. Error-Correcting Codes with Byte Error-Detection Capability , 1983, IEEE Trans. Computers.
[11] C. L. Chen,et al. Symbol Error-Correcting Codes for Computer Memory Systems , 1992, IEEE Trans. Computers.
[12] Chin-Long Chen,et al. Error-correcting codes for byte-organized memory systems , 1986, IEEE Trans. Inf. Theory.
[13] Howard Leo Kalter,et al. A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC , 1990 .
[14] W. Edwin Clark,et al. The construction of some bit and byte error control codes using partial Steiner systems , 1989, IEEE Trans. Inf. Theory.
[15] Cristina Silvano,et al. Construction techniques for systematic SEC-DED codes with single byte error detection and partial correction capability for computer memory systems , 1995, IEEE Trans. Inf. Theory.
[16] Eiji Fujiwara,et al. Single Byte Error Correcting—Double Byte Error Detecting Codes for Memory Systems , 1982, IEEE Transactions on Computers.
[17] Sudhakar M. Reddy. A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems , 1978, IEEE Transactions on Computers.
[18] L Shen,et al. SINGLE BYTE ERROR CORRECTING DOUBLE BYTE ERROR DETECTING CODES , 1982 .
[19] Eiji Fujiwara,et al. Error-control coding for computer systems , 1989 .