Implementing and evaluating adiabatic arithmetic units

In recent years, several adiabatic logic architectures have been proposed for low-power VLSI design. However, no work has been presented describing the implementation and evaluation of nontrivial adiabatic circuits. We have evaluated a specific adiabatic architecture and used it in the design of low-power arithmetic units. We investigated implementation issues specific to adiabatic system development and performed a systematic comparison of our designs with corresponding CMOS circuits. In this paper we describe our adiabatic designs, discuss implementation issues at the logic and architectural level, and report our empirical findings.

[1]  A. Kramer,et al.  Adiabatic Computing with the 2n-2n2d Logic Family , 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

[2]  John Stewart Denker,et al.  Adiabatic dynamic logic , 1995 .

[3]  Martin F. Schlecht,et al.  Recovered energy logic-A highly efficient alternative to today's logic circuits , 1993, Proceedings of IEEE Power Electronics Specialist Conference - PESC '93.

[4]  S. Younis,et al.  Practical implementation of charge recovering asymptotically zero power CMOS , 1993 .

[5]  John S. Denker,et al.  2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits , 1995, ISLPED '95.

[6]  John Stewart Denker,et al.  Adiabatic dynamic logic , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[7]  Thomas F. Knight,et al.  Asymptotically Zero Energy Split-Level Charge Recovery Logic , 1994 .