AN EXPLICIT CROSSTALK AWARE DELAY MODELLING FOR ON-CHIP VLSI RLC INTERCONNECT WITH SKIN EFFECT

This paper presents a novel analytical closed form expression for the crosstalk noise voltage and delay in the presence of skin effect. With the rapid development of high frequency IC technology, a number of high-speed interconnect effects, such as ringing, signal delay, distortion, reflections, and crosstalk, need to be considered during the IC design. Skin effect is one of the high frequency phenomena that can adversely affect the distribution of current density in interconnect because the problem associated with the skin effect is that it attenuates the high frequency components of a signal more than that of the low frequency components. On-Chip interconnect has become the dominant factor in deep sub-micrometer (DSM) integrated circuits (ICs). With increasing levels of on-chip integration, more functional units are integrated onto a single die, such as a multi-core microprocessor and a system-on-chip. Global interconnect, which acts as a communication media among these functional units, plays an increasingly important role and can significantly limit the performance of advanced systems. Accurate noise and delay modelling for RLC lines is thus critical for timing and signal integrity analysis. Skin effect basically affects the resistance and also the inductance, which in turn affects the system integrity in particular and its response as a whole. The current distribution inside the conductor changes as frequency increases. These changes produced in the conductors are known as skin effect. Till now the skin effect has been neglected for the modelling of the on-chip interconnects. But with the increase in frequency to the GHz range, the skin effect has become prominent in performance parameter modelling. In this paper, firstly a crosstalk noise formula for on chip VLSI interconnect has been proposed without considering the skin effect. The voltage response at the output node is analytically derived and then the skin effect on the line resistance is analysed. In this work, the resistance variation due to the skin effect is considered in two wire transmission line model. An explicit closed form expression has been developed for the estimation of cross-talk noise voltage and delay. The correlation between the skin effect and the noise induced is also discussed. The simulation results justify the efficacy of the proposed crosstalk noise aware delay model in the presence of skin effect.

[1]  S. Wong,et al.  Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design , 2001, IEEE J. Solid State Circuits.

[2]  Rajib Kar,et al.  Accurate Crosstalk Analysis for RLC On-Chip VLSI Interconnect , 2011 .

[3]  Yehea I. Ismail,et al.  Efficient model order reduction including skin effect , 2003, DAC '03.

[4]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[5]  Yehea I. Ismail,et al.  Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[6]  G. Le Carval,et al.  Extraction of (R,L,C,G) interconnect parameters in 2D transmission lines using fast and efficient numerical tools , 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).

[7]  Eby G. Friedman,et al.  Optimum wire sizing of RLC interconnect with repeaters , 2003, GLSVLSI '03.

[8]  Rajib Kar,et al.  Coupling Aware Explicit Delay Metric for On- Chip RLC Interconnect for Ramp input , 2010 .

[9]  Rajib Kar,et al.  An Explicit Delay Model for On-Chip VLSI RLC Interconnect , 2011, 2011 International Conference on Devices and Communications (ICDeCom).

[10]  D. P. Neikirk,et al.  Compact equivalent circuit model for the skin effect , 1996, 1996 IEEE MTT-S International Microwave Symposium Digest.

[11]  R. L. Wigington,et al.  Transient Analysis of Coaxial Cables Considering Skin Effect , 1957, Proceedings of the IRE.

[12]  Larry Pileggi,et al.  IC Interconnect Analysis , 2002 .

[13]  G. H. Massiha,et al.  Accurate modeling of thin-film inductance for nano-chip , 2003, 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003..

[14]  S. Nikolaidis,et al.  Delay and power estimation for a CMOS inverter driving RC interconnect loads , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[15]  H. T. Kohlhaas,et al.  Reference data for radio engineers , 1943 .

[16]  Lei Wang,et al.  A practical approach to modeling skin effect in on-chip interconnects , 2004, GLSVLSI '04.

[17]  Rajib Kar,et al.  Explicit Delay and Power Estimation Method for CMOS Inverter Driving on-Chip RLC Interconnect Load , 2011 .

[18]  Chu-Sun Yen,et al.  Time-domain skin-effect model for transient analysis of lossy transmission lines , 1982, Proceedings of the IEEE.

[19]  B. K. Sen,et al.  Skin effects models for transmission line structures using generic SPICE circuit simulators , 1998, IEEE 7th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.98TH8370).

[20]  H. A. Wheeler.  Formulas for the Skin Effect , 1942, Proceedings of the IRE.

[21]  L. Gal,et al.  On-chip cross talk-the new signal integrity challenge , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[22]  Rajib Kar,et al.  An Efficient Dynamic Power Estimation Method for On-chip VLSI Interconnects , 2011, 2011 Second International Conference on Emerging Applications of Information Technology.

[23]  Rajib Kar,et al.  CLOSED FORM SOLUTION FOR DELAY AND POWER FOR A CMOS INVERTER DRIVING RLC INTERCONNECT UNDER STEP INPUT , 2011 .