Utilizing Power Management and Timing Slack for Low Power in High-Level Synthesis

As the design size continues to increase, low power has become a very important concern. In the high-level synthesis stage, operation scheduling is critical for circuit performance. Previous algorithms do not consider power management and timing slack (operation delay selection) at the same time. Different from previous works, in this paper, we utilize power management and timing slack as possible to reduce the total power under the overall latency constraint. We propose an integer linear programming (ILP) approach to combine operation scheduling, power management, and timing slack selection in order to reduce the total power. Benchmark circuits show that our ILP approach has a significant improvement.