THE DESIGN OF A VERY HIGH PERFORMANCE IIR FILTER CHIP

The design of a high performance bit parallel second order IIR filter chip is described. The chip in question is highly pipelined, uses most significant digit first arithmetic and consists mainly of arrays of simple carry–save adders. It has been fabricated in 1.5 μm double level metal CMOS technology, accepts 12 bit input data and coefficient values and can operate at up to 40 megasamples per second. All data inputs and outputs are in two's complement form and the chip power consumption is 1 W. The highly regular nature of the architecture has been exploited for test pattern generation. It is shown how small, but important modifications to the basic architecture, can significantly improve testing. As a result, 100% fault coverage can be achieved using less than 1000 test vectors. The chip may be used in a cascade realisation to form a general Nth order filter.