A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS

A bit-serial architecture for multi-Gbps LDPC decoding is demonstrated to alleviate the routing congestion which is the main limitation for LDPC decoders. We report on a 3.3-Gbps 0.13-μm CMOS prototype. It occupies 7.3-mm2 core area with 1416-mW maximum power consumption from a 1.2-V supply. We demonstrate how early termination and supply voltage scaling can improve the decoder energy efficiency. Finally, the same architecture is applied to a (2048, 1723) LDPC code compliant with the 10GBase-T standard.

[1]  C. Plett,et al.  A 0.18-$muhbox m$CMOS Analog Min-Sum Iterative Decoder for a (32,8) Low-Density Parity-Check (LDPC) Code , 2006, IEEE Journal of Solid-State Circuits.

[2]  Frank R. Kschischang,et al.  A bit-serial approximate min-sum LDPC decoder and FPGA implementation , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[3]  Evangelos Eleftheriou,et al.  Regular and irregular progressive edge-growth tanner graphs , 2005, IEEE Transactions on Information Theory.

[4]  Mohammad M. Mansour,et al.  A 640-Mb/s 2048-bit programmable LDPC decoder chip , 2006, IEEE Journal of Solid-State Circuits.

[5]  Masoud Ardakani,et al.  Gear-shift decoding , 2006, IEEE Transactions on Communications.

[6]  Ching-Che Chung,et al.  A 480Mb/s LDPC-COFDM-based UWB baseband transceiver , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[7]  A. Blanksby,et al.  A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.

[8]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[9]  A. J. Blanksby,et al.  A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.