Prediction-based superpage-friendly TLB designs
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[1] Margaret Martonosi,et al. Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors , 2009, 2009 18th International Conference on Parallel Architectures and Compilation Techniques.
[2] Thomas A. Ziaja,et al. Sparc T4: A Dynamically Threaded Server-on-a-Chip , 2012, IEEE Micro.
[3] André Seznec. A New Case for Skewed-Associativity , 1997 .
[4] Anand Sivasubramaniam,et al. Going the distance for TLB prefetching: an application-driven study , 2002, ISCA.
[5] Babak Falsafi,et al. Clearing the clouds: a study of emerging scale-out workloads on modern hardware , 2012, ASPLOS XVII.
[6] Per Hammarlund,et al. 4th generation Intel™ Core processor, codenamed Haswell , 2013, 2013 IEEE Hot Chips 25 Symposium (HCS).
[7] Christian Bienia,et al. Benchmarking modern multiprocessors , 2011 .
[8] Alan L. Cox,et al. Practical, transparent operating system support for superpages , 2002, OPSR.
[9] Alan L. Cox,et al. Translation caching: skip, don't walk (the page table) , 2010, ISCA.
[10] André Seznec,et al. A case for two-way skewed-associative caches , 1993, ISCA '93.
[11] Thomas F. Wenisch,et al. SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture , 2004, PERV.
[12] Margaret Martonosi,et al. Inter-core cooperative TLB for chip multiprocessors , 2010, ASPLOS XV.
[13] Margaret Martonosi,et al. Inter-core cooperative TLB for chip multiprocessors , 2010, ASPLOS 2010.
[14] Mark D. Hill,et al. Tradeoffs in supporting two page sizes , 1992, ISCA '92.
[15] Alan L. Cox,et al. SpecTLB: A mechanism for speculative address translation , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).
[16] Per Stenström,et al. Recency-based TLB preloading , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).
[17] Mahmut T. Kandemir,et al. Synergistic TLBs for High Performance Address Translation in Chip Multiprocessors , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.
[18] Gabriel H. Loh,et al. Increasing TLB reach by exploiting clustering in page translations , 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).
[19] Jung Ho Ahn,et al. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[20] Fredrik Larsson,et al. Simics: A Full System Simulation Platform , 2002, Computer.
[21] Aamer Jaleel,et al. CoLT: Coalesced Large-Reach TLBs , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.
[22] Margaret Martonosi,et al. Shared last-level TLBs for chip multiprocessors , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.
[23] Mark D. Hill,et al. Surpassing the TLB performance of superpages with less operating system support , 1994, ASPLOS VI.
[24] Michael M. Swift,et al. Efficient virtual memory for big memory servers , 2013, ISCA.