Exploring the algorithmic design space using high level synthesis

HYPER is a high level synthesis system, targeted at numerically intensive applications. By shifting the emphasis from the traditional high level synthesis tasks (such as scheduling and assignment) to the domain of transformations, new venues for high level synthesis are opened. One of the most exciting among them, with potentially the largest impact on the quality of the design, is design and selection of the algorithms for a given application. After a brief overview of the HYPER system, the authors concentrate on the exploration of the algorithmic design space. They show how HYPER can improve the performance or cost of real life applications with orders of magnitude by guiding and conducting a proper algorithmic design selection process.<<ETX>>

[1]  Pierre G. Paulin,et al.  Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Alice C. Parker,et al.  The high-level synthesis of digital systems , 1990, Proc. IEEE.

[3]  Robert A. Walker,et al.  A Survey of high-level synthesis systems , 1991 .

[4]  Miodrag Potkonjak,et al.  Maximally fast and arbitrarily fast implementation of linear computations , 1992, ICCAD '92.

[5]  Jan M. Rabaey,et al.  DSP specification using the Silage language , 1990 .

[6]  Alice C. Parker,et al.  An Abstract Model of Behavior for Hardware Descriptions , 1983, IEEE Transactions on Computers.

[7]  Michael Wolfe,et al.  The Tiny Loop Restructuring Research Tool , 1991, ICPP.

[8]  William J. Dally Micro-optimization of floating-point operations , 1989, ASPLOS 1989.

[9]  A. Gray,et al.  Digital lattice and ladder filter synthesis , 1973 .

[10]  Alfred V. Aho,et al.  Principles of Compiler Design , 1977 .

[11]  Daniel Gajski,et al.  Automatic Design with Dependence Graphs , 1980, 17th Design Automation Conference.

[12]  Miodrag Potkonjak,et al.  Resource driven synthesis in the HYPER system , 1990, IEEE International Symposium on Circuits and Systems.

[13]  Jan M. Rabaey,et al.  Hierarchical scheduling of DSP programs onto multiprocessors for maximum throughput , 1992, [1992] Proceedings of the International Conference on Application Specific Array Processors.

[14]  Miodrag Potkonjak,et al.  Pipelining: just another transformation , 1992, [1992] Proceedings of the International Conference on Application Specific Array Processors.

[15]  Joos Vandewalle,et al.  An efficient microcode compiler for application specific DSP processors , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Alan V. Oppenheim,et al.  Discrete-Time Signal Pro-cessing , 1989 .

[17]  Donald E. Thomas,et al.  Behavioral transformation for algorithmic level IC design , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[19]  S. Mitra,et al.  Canonic realizations of digital filters using the continued fraction expansion , 1972 .

[20]  Henry Massalin Superoptimizer: a look at the smallest program , 1987, ASPLOS 1987.

[21]  Daniel P. Siewiorek,et al.  A Technology-Relative Computer-Aided Design System: Abstract Representations, Transformations, and Design Tradeoffs , 1978, 15th Design Automation Conference.

[22]  J. Barnett A vocal data management system , 1973 .

[23]  Sanjit K. Mitra,et al.  A general family of multivariable digital lattice filters , 1985 .

[24]  Sanjit K. Mitra,et al.  Digital ladder networks , 1973 .

[25]  Richard I. Hartley,et al.  Tree-height minimization in pipelined architectures , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[26]  Wayne Wolf,et al.  High-Level VLSI Synthesis , 1991 .

[27]  Ioannis Pitas,et al.  Nonlinear Digital Filters - Principles and Applications , 1990, The Springer International Series in Engineering and Computer Science.

[28]  Miodrag Potkonjak,et al.  Fast prototyping of datapath-intensive architectures , 1991, IEEE Design & Test of Computers.

[29]  Wayne Wolf,et al.  Architectural Optimization Methods for Control-Dominated Machines , 1991 .

[30]  Srinivas Devadas,et al.  Algorithms for hardware allocation in data path synthesis , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[31]  Miodrag Potkonjak,et al.  HYPER-LP: a system for power minimization using architectural transformations , 1992, ICCAD 1992.

[32]  H. Nussbaumer Fast Fourier transform and convolution algorithms , 1981 .

[33]  K. Yao,et al.  A class of systolizable IIR digital filters and its design for proper scaling and minimum output roundoff noise , 1990 .

[34]  Thomas Kailath,et al.  Orthogonal digital filters for VLSI implementation , 1984 .

[35]  Clifford T. Mullis,et al.  Synthesis of minimum roundoff noise fixed point digital filters , 1976 .

[36]  Hugo De Man Design technology research for the nineties: more of the same? , 1992, EURO-DAC.

[37]  Miodrag Potkonjak,et al.  An integrated system for rapid prototyping of high performance algorithm specific data paths , 1992, [1992] Proceedings of the International Conference on Application Specific Array Processors.

[38]  Donald E. Knuth,et al.  Sorting and Searching , 1973 .

[39]  David G. Messerschmitt,et al.  Breaking the Recursive Bottleneck , 1988 .

[40]  Richard E. Blahut,et al.  Fast Algorithms for Digital Signal Processing , 1985 .

[41]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[42]  P. Yip,et al.  Discrete Cosine Transform: Algorithms, Advantages, Applications , 1990 .

[43]  Miodrag Potkonjak Algorithms for high-level synthesis: resource utilization-based approach , 1992 .

[44]  Robert W. Brodersen Anatomy of a Silicon Compiler , 1992 .

[45]  Mohamed I. Elmasry,et al.  Architectural synthesis for DSP silicon compilers , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[46]  Jayaram Bhasker,et al.  An optimizer for hardware synthesis , 1990, IEEE Design & Test of Computers.

[47]  J. Ortega Numerical Analysis: A Second Course , 1974 .

[48]  Yu-Chin Hsu,et al.  Scheduling for functional pipelining and loop winding , 1991, 28th ACM/IEEE Design Automation Conference.

[49]  Alice C. Parker,et al.  Sehwa: a software package for synthesis of pipelines from behavioral specifications , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[50]  Howard Trickey,et al.  Flamel: A High-Level Hardware Compiler , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[51]  Donald Ervin Knuth,et al.  The Art of Computer Programming , 1968 .

[52]  A.V. Oppenheim,et al.  Analysis of linear digital networks , 1975, Proceedings of the IEEE.

[53]  Charles N. Fischer,et al.  Crafting a Compiler , 1988 .

[54]  A. Fettweis Wave digital filters: Theory and practice , 1986, Proceedings of the IEEE.

[55]  Jacob Shekel Analysis of linear networks , 1957 .

[56]  E. Avenhaus On the design of digital filters with coefficients of limited word length , 1972 .

[57]  David J. Goodman,et al.  Personal Communications , 1994, Mobile Communications.