SEU Tolerant Memory Using Error Correction Code

With decreasing circuit lithography dimensions and increasing memory densities, an SEU may affect multiple adjacent memory cells. This paper presents an SEU hardened memory using error correction code that can correct single errors, double-adjacent errors, triple-adjacent errors and double-almost-adjacent errors. The proposed memory introduces small area, power and delay overheads.

[1]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[2]  Tatiana Kalganova,et al.  Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness , 1999, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware.

[3]  Pedro Reviriego,et al.  Matrix-Based Codes for Adjacent Error Correction , 2010, IEEE Transactions on Nuclear Science.

[4]  Peter Hazucha,et al.  Characterization of soft errors caused by single event upsets in CMOS processes , 2004, IEEE Transactions on Dependable and Secure Computing.

[5]  Tomoyuki Ishida,et al.  A novel states recovery technique for the TMR softcore processor , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[6]  Hideo Ito,et al.  Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Aabhas Rastogi,et al.  SEU MITIGATION-using 1/3 rate convolution coding , 2009, 2009 2nd IEEE International Conference on Computer Science and Information Technology.

[8]  Tapan J. Chakraborty,et al.  A TMR Scheme for SEU Mitigation in Scan Flip-Flops , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[9]  Kartik Mohanram,et al.  Gate sizing to radiation harden combinational logic , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Mikel Azkarate-askasua,et al.  A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[11]  A.F. Witulski,et al.  Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs , 2007, IEEE Transactions on Nuclear Science.

[12]  J.G. Delgado-Frias,et al.  Delay and Energy Analysis of SEU and SET-Tolerant Pipeline Latches and Flip-Flops , 2009, IEEE Transactions on Nuclear Science.

[13]  Yu Cao,et al.  New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[14]  Ming Zhu,et al.  Efficient Two-Dimensional Error Codes for Multiple Bit Upsets Mitigation in Memory , 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

[15]  Sunil P. Khatri,et al.  A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements , 2008, 2008 Design, Automation and Test in Europe.

[16]  Christos A. Papachristou,et al.  SRAM Cell Design Protected from SEU Upsets , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[17]  peixiong zhao,et al.  Reliability and radiation effects in IC technologies , 2008, 2008 IEEE International Reliability Physics Symposium.

[18]  Robert Baumann,et al.  Soft errors in advanced computer systems , 2005, IEEE Design & Test of Computers.

[19]  Ahmad Patooghy,et al.  Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies , 2007, 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07).

[20]  H.J. Tausch.  Simplified Birthday Statistics and Hamming EDAC , 2009, IEEE Transactions on Nuclear Science.

[21]  Charles E. Stroud.  Reliability of majority voting based VLSI fault-tolerant circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[22]  Ricardo Reis,et al.  An automatic technique for optimizing Reed-Solomon codes to improve fault tolerance in memories , 2005, IEEE Design & Test of Computers.

[23]  Dan Alexandrescu,et al.  Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors , 2008, 26th IEEE VLSI Test Symposium (vts 2008).