Architecture of the parallel recirculating pipeline

Current image analysis and image understanding applications in DoD systems require very high performance image pixel processing in real time. To attain the necessary performance within stringent system size weight and power constraints requires special-purpose parallel processing hardware architectures. At the same time it is desirable to retain as much programmability as possible in order to rapidly adapt the hardware to new applications or evolving system requirements. The Parallel Recirculating Pipeline processor uses techniques adopted from image algebra and mathematical morphology to provide a low-cost low-complexity high-performance architecture that is suitable for silicon implementation and programmable in high-order languages. The parallel recirculating pipeline hardware architecture is based on a cellular array structure in which each cell is a pipelined neighborhood processor. Each processor cell transforms an entire image segment by successively executing an operation on small fixed-size neighborhoods around each pixel. By cascading a series of these operations transforms on larger neighborhoods can be achieved. The parallel recirculating pipeline achieves cascading by allowing a series of cells to be connected in a pipelined fashion. Partial results can recirculate several times through the hardware pipeline via an external buffer memory. A virtual pipeline of any length is thus achieved. Several novel features of the architecture allow multiple pipelines to operate in parallel on strips of the same image. These features can support parallel expansion to a large number of processors with correspondingly