Architecture design and performance analysis of practical buffered-crossbar packet switches

ARCHITECTURE DESIGN AND PERFORMANCE ANALYSIS OF PRACTICAL BUFFERED-CROSSBAR PACKET SWITCHES by Ziqian Dong Combined input crosspoint buffered (CICB) packet switches were introduced to relax inputoutput arbitration timing and provide high throughput under admissible traffic. However, the amount of memory required in the crossbar of an N x N switch is N2 x k x L, where k is the crosspoint buffer size and needs to be of size RTT in cells, L is the packet size. RTT is the round-trip time which is defined by the distance between line cards and switch fabric. When the switch size is large or RTT is not negligible, the memory amount required makes the implementation costly or infeasible for buffered crossbar switches. To reduce the required memory amount, a family of shared memory combined-input crosspoint-buffered (SMCB) packet switches, where the crosspoint buffers are shared among inputs, are introduced in this thesis. One of the proposed switches uses a memory speedup of 711 and dynamic memory allocation, and the other switch avoids speedup by arbitrating the access of inputs to the crosspoint buffers. These two switches reduce the required memory of the buffered crossbar by 50% or more and achieve equivalent throughput under independent and identical traffic with uniform distributions when using random selections. The proposed mSMCB switch is extended to support differentiated services and long RTT. To support P traffic classes with different priorities, CICB switches have been reported to use N 2 x k x L x P amount of memory to avoid blocking of high priority cells. The proposed SMCB switch with support for differentiated services requires 1/mP of the memory amount in the buffered crossbar and achieves similar throughput performance to that of a CICB switch with similar priority management, while using no speedup in the shared memory. The throughput performance of SMCB switch with crosspoint buffers shared by inputs (I-SMCB) is studied under multicast traffic. An output-based shared-memory crosspointbuffered (O-SMCB) packet switch is proposed where the crosspoint buffers are shared by two outputs and use no speedup. The proposed O-SMCB switch provides high performance under admissible uniform and nonuniform multicast traffic models while using 50% of the memory used in CICB switches. Furthermore, the O-SMCB switch provides higher throughput than the I-SMCB switch. As SMCB switches can efficiently support an RTT twice as long as that supported by CICB switches and as the performance of SMCB switches is bounded by a matching between inputs and crosspoint buffers, a new family of CICB switches with flexible access to crosspoint buffers are proposed to support longer RTTs than SMCB switches and to provide higher throughput under a wide variety of admissible traffic models. The CICB switches with flexible access allow an input to use any available crosspoint buffer at a given output. The proposed switches reduce the required crosspoint buffer size by a factor of N, keep the service of cells in sequence, and use no speedup. This new class of switches achieve higher throughput performance than CICB switches under a large variety of traffic models, while supporting long RTTs. Crosspoint buffered switches that are implemented in single chips have limited scalability. To support a large number of ports in crosspoint buffered switches, memorymemory-memory (MMM) Clos-network switches are an alternative. The MMM switches that use minimum memory amount at the central module is studied. Although, this switch can provide a moderate throughput, MMM switch may serve cells out of sequence. As keeping cells in sequence in an MMM switch may require buffers be distributed per flow, an MMM with extended memory in the switch modules is studied. To solve the out of sequence problem in MMM switches, a queuing architecture is proposed for an MMM switch. The service of cells in sequence is analyzed. ARCHITECTURE DESIGN AND PERFORMANCE ANALYSIS OF PRACTICAL BUFFERED-CROSSBAR PACKET SWITCHES

[1]  Thomas E. Anderson,et al.  High-speed switch scheduling for local-area networks , 1993, TOCS.

[2]  Nick McKeown,et al.  Designing packet buffers with statistical guarantees , 2004, Proceedings. 12th Annual IEEE Symposium on High Performance Interconnects.

[3]  K. Yoshigoe.  A parallel-polled virtual output queue with a buffered crossbar , 2001 .

[4]  Naoaki Yamanaka,et al.  High-speed ATM switch with input and cross-point buffers , 1993 .

[5]  R. Rojas-Cessa,et al.  CIXB-1: combined input-one-cell-crosspoint buffered switch , 2001, 2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552).

[6]  Cyriel Minkenberg,et al.  A four-terabit single-stage packet switch with large round-trip time support , 2002, Proceedings 10th Symposium on High Performance Interconnects.

[7]  Roberto Rojas-Cessa,et al.  Long round-trip time support with shared-memory crosspoint buffered packet switch , 2005, 13th Symposium on High Performance Interconnects (HOTI'05).

[8]  Eiji Oki,et al.  Round-robin selection with adaptable-size frame in a combined input-crosspoint buffered switch , 2003, IEEE Communications Letters.

[9]  Eiji Oki,et al.  A 10Gb / s ( 1 . 25 Gb / s 8 ) 4 2 0 . 25m CMOS / SIMOX ATM Switch Based on Scalable Distributed Arbitration , 1999 .

[10]  Masayoshi Nabeshima.  Performance Evaluation of a Combined Input- and Crosspoint-Queued Switch , 2000 .

[11]  W. David Sincoskie,et al.  Sunshine: A High-Performance Self-Routing Broadband Packet Switch Architecture , 1991, IEEE J. Sel. Areas Commun..

[12]  F. M. Chiussi,et al.  Low-cost scalable switching solutions for broadband networking: the ATLANTA architecture and chipset , 1997 .

[13]  Eiji Oki,et al.  Broadband Packet Switching Technologies: A Practical Guide to ATM Switches and IP Routers , 2001 .

[14]  Hung-Hsiang Jonathan Chao,et al.  Next generation routers , 2002, Proc. IEEE.

[15]  Carl M. Harris,et al.  Fundamentals of queueing theory (2nd ed.). , 1985 .

[16]  Roberto Rojas-Cessa,et al.  OSPF-Based Adaptive and Flexible Security-Enhanced QoS Provisioning , 2006, 2006 IEEE Sarnoff Symposium.

[17]  Mark J. Karol,et al.  Queueing in high-performance packet switching , 1988, IEEE J. Sel. Areas Commun..

[18]  David W. Petr,et al.  Input-queued switch based on a scheduling algorithm , 1995 .

[19]  Zhen Zhou,et al.  Space-memory-memory architecture for CLOS-network packet switches , 2005, IEEE International Conference on Communications, 2005. ICC 2005. 2005.

[20]  Fouad A. Tobagi,et al.  Architecture, Performance, and Implementation of the Tandem Banyan Fast Packet Switch , 1991, IEEE J. Sel. Areas Commun..

[21]  Mounir Hamdi,et al.  Practical scheduling algorithms for high-performance packet switches , 2003, IEEE International Conference on Communications, 2003. ICC '03..

[22]  McKeownNick.  The iSLIP scheduling algorithm for input-queued switches , 1999 .

[23]  Symeon Papavassiliou,et al.  A flexible and distributed architecture for adaptive end-to-end QoS provisioning in next-generation networks , 2005, IEEE Journal on Selected Areas in Communications.

[24]  Guansong Zhang,et al.  TrueWay: a highly scalable multi-plane multi-stage buffered packet switch , 2005, HPSR. 2005 Workshop on High Performance Switching and Routing, 2005..

[25]  Andrea Bianco,et al.  Frame-based matching algorithms for input-queued switches , 2002, Workshop on High Performance Switching and Routing, Merging Optical and IP Technologie.

[26]  Nick McKeown,et al.  Maintaining packet order in two-stage switches , 2002, Proceedings.Twenty-First Annual Joint Conference of the IEEE Computer and Communications Societies.

[27]  Cyriel Minkenberg,et al.  Reducing memory size in buffered crossbars with large internal flow control latency , 2003, GLOBECOM '03. IEEE Global Telecommunications Conference (IEEE Cat. No.03CH37489).

[28]  Manolis Katevenis,et al.  Scheduling in Non-Blocking Buffered Three-Stage Switching Fabrics , 2006, Proceedings IEEE INFOCOM 2006. 25TH IEEE International Conference on Computer Communications.

[29]  Cheng-Shang Chang,et al.  Load balanced Birkhoff-von Neumann switches , 2001, 2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552).

[30]  Seyed Mostafa Safavi,et al.  The optimized prioritized iSLIP scheduling algorithm for input-queued switches with ability to support multiple priority levels , 2003, 10th International Conference on Telecommunications, 2003. ICT 2003..

[31]  Ioannis Papaefstathiou,et al.  Variable packet size buffered crossbar (CICQ) switches , 2004, 2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577).

[32]  Cyriel Minkenberg,et al.  10 A Four-Terabit Packet Switch Supporting Long Round-Trip Times , 2003, IEEE Micro.

[33]  Tony T. Lee,et al.  Non-blocking copy networks for multicast packet switching , 1988, 1988 International Zurich Seminar on Digital Communications - Mapping New Applications onto New Technologies. Proceedings.

[34]  Eiji Oki,et al.  Concurrent round-robin-based dispatching schemes for Clos-network switches , 2002, TNET.

[35]  Charles Clos,et al.  A study of non-blocking switching networks , 1953 .

[36]  Kumar,et al.  Advanced Router Architectures , 2006 .

[37]  Devavrat Shah,et al.  Maximal matching scheduling is good enough , 2003, GLOBECOM '03. IEEE Global Telecommunications Conference (IEEE Cat. No.03CH37489).

[38]  Paolo Giaccone,et al.  Randomized scheduling algorithms for high-aggregate bandwidth switches , 2003, IEEE J. Sel. Areas Commun..

[39]  Ge Nong,et al.  Analysis of nonblocking ATM switches with multiple input queues , 1999, TNET.

[40]  Mounir Hamdi,et al.  MCBF: a high-performance scheduling algorithm for buffered crossbar switches , 2003, IEEE Communications Letters.

[41]  Balaji Prabhakar,et al.  The throughput of data switches with and without speedup , 2000, Proceedings IEEE INFOCOM 2000. Conference on Computer Communications. Nineteenth Annual Joint Conference of the IEEE Computer and Communications Societies (Cat. No.00CH37064).

[42]  Jean C. Walrand,et al.  Achieving 100% throughput in an input-queued switch , 1996, Proceedings of IEEE INFOCOM '96. Conference on Computer Communications.

[43]  Roberto Rojas-Cessa,et al.  Load-balanced combined input-crosspoint buffered packet switch and long round-trip times , 2005, IEEE Communications Letters.

[44]  S. Vassiliadis,et al.  Integrating uni- and multicast scheduling in buffered crossbar switches , 2006, 2006 Workshop on High Performance Switching and Routing.

[45]  Mounir Hamdi,et al.  Static round-robin dispatching schemes for Clos-network switches , 2002, Workshop on High Performance Switching and Routing, Merging Optical and IP Technologie.

[46]  Mounir Hamdi,et al.  Scheduling multicast traffic in internally buffered crossbar switches , 2004, 2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577).

[47]  S. Sessa,et al.  Practical algorithms for multicast support in input queued switches , 2006, 2006 Workshop on High Performance Switching and Routing.