Parallel algorithms and architectures for VLSI pattern generation

The process of data preparation for pattern generation consists of the performing of various geometric operations upon a user's design. This is the final manipulation of the design prior to the making of the masks and can be exceptionally time consuming, especially when a very large user designs are being processed. This thesis addresses one way of speeding up the processing by the use of (relatively) small numbers of loosely coupled processors as a multiprocessing unit. The starting point of the work was commercial pattern generation system. This incorporated programs programs or modules to perform parsing and flattening, overlap removal (merging) and partitioning. The major results are a series of performance measurements obtained by emulating parallel processors with an appropriate interconnection pattern. These give a valuable indication of the degree of performance enhancement which this approach to parallelism may be expected to bring. Confirmation of these expectations via practical implementations on two varieties of workstation clusters is reported. The three major parts of a Pattern Generation system, the merge stage whose most important aspect is overlap removal and sizing, and the decomposition and sort (termed fracture) for the two major types of lithographical equipment (electron-beam and photo-mechanical) are examined separately. Particular emphasis is placed on the merge stage, which is the most time critical part of the whole process. The method used to partition the merge task among processors is area subdivision. The practical work carried out consisted of devising practical algorithms for the area subdivision and recombination, and in the setting up of test harnesses multiprocessor emulations.