MRAM Cell Technology for Over 500-MHz SoC
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N. Sakimura | H. Honjo | S. Saito | S. Tahara | T. Sugibayashi | T. Suzuki | T. Honda | N. Ishiwata | Tetsuhiro Suzuki | N. Ishiwata | H. Honjo | S. Saito | S. Tahara | N. Sakimura | T. Sugibayashi | T. Honda
[1] Kinam Kim,et al. Highly scalable MRAM using field assisted current induced switching , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
[2] Hiroaki Yoda,et al. Resistance ratio read (R/sup 3/) architecture for a burst operated 1.5V MRAM macro , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..
[3] N. Sakimura,et al. MRAM-writing circuitry to compensate for thermal-variation of magnetization-reversal current , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).
[4] H. Hoenigschmid,et al. A high-speed 128-kb MRAM core for future universal memory applications , 2004, IEEE Journal of Solid-State Circuits.
[5] H. Hoenigschmid,et al. A 16-Mb MRAM featuring bootstrapped write drivers , 2005, IEEE Journal of Solid-State Circuits.
[6] K. Tsunekawa,et al. 230% room temperature magnetoresistance in CoFeB/MgO/CoFeB magnetic tunnel junctions , 2005, INTERMAG Asia 2005. Digests of the IEEE International Magnetics Conference, 2005..
[7] R. Scheuerlein,et al. A 10 ns read and write non-volatile memory array using a magnetic tunnel junction and FET switch in each cell , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
[8] M. Nakayama,et al. A 16Mb MRAM with FORK Wiring Scheme and Burst Modes , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
[9] J. Otani,et al. A 1.2V 1Mbit embedded MRAM core with folded bit-line array architecture , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).
[10] P. Brown,et al. 90nm toggle MRAM array with 0.29/spl mu/m/sup 2/ cells , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
[11] M. Aoki,et al. A novel voltage sensing 1T/2MTJ cell with resistance ratio for highly stable and scalable MRAM , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..
[12] A. Omair,et al. A 4-Mb 0.18-/spl mu/m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers , 2005, IEEE Journal of Solid-State Circuits.
[13] Heinz Hoenigschmid,et al. Signal-Margin-Screening for Multi-Mb MRAM , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
[14] Saied N. Tehrani,et al. A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects , 2003, IEEE J. Solid State Circuits.
[15] M. Durlam,et al. Nonvolatile RAM based on magnetic tunnel junction elements , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
[16] Stefan Doll,et al. MRAM and microprocessor system-in-package: technology stepping stone to advanced embedded devices , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).