Tapered Floating Point: A New Floating-Point Representation

It is well known that there is a possible tradeoff in the binary representation of floating-point numbers in which one bit of accuracy can be gained at the cost of halving the exponent range, and vice versa. A way in which the exponent range can be greatly increased while preserving full accuracy for most computations is suggested.

[1]  Benjamin Arthur Laws A parallel BCH decoder , 1970 .

[2]  Stephen S. Yau,et al.  Fault Diagnosis and Repair of Cutpoint Cellular Arrays , 1970, IEEE Transactions on Computers.

[3]  William H. Kautz,et al.  Fault Testing and Diagnosis in Combinational Digital Circuits , 1968, IEEE Transactions on Computers.

[4]  Karl N. Levitt,et al.  Cellular Interconnection Arrays , 1968, IEEE Transactions on Computers.

[5]  Karl N. Levitt,et al.  Cellular arrays for the parallel implementation of binary error-correcting codes , 1969, IEEE Trans. Inf. Theory.

[6]  William H. Kautz,et al.  Cellular Logic-in-Memory Arrays , 1969, IEEE Transactions on Computers.

[7]  Robert C. Minnick Cutpoint Cellular Logic , 1964, IEEE Trans. Electron. Comput..

[8]  Elwyn R. Berlekamp,et al.  Algebraic coding theory , 1984, McGraw-Hill series in systems science.

[9]  Kenneth James Thurber Fault Location in Cellular Arrays , 1899 .

[10]  R. Gallager Information Theory and Reliable Communication , 1968 .