Formally Defining and Verifying Master/Slave Speculative Parallelization
暂无分享,去创建一个
[1] José Meseguer,et al. The Maude LTL Model Checker and Its Implementation , 2003, SPIN.
[2] MeseguerJosé. Conditional rewriting logic as a unified model of concurrency , 1992 .
[3] J. Meseguer,et al. Building Equational Proving Tools by Reflection in Rewriting Logic , 2000 .
[4] Jun Sawada,et al. Processor Verification with Precise Exeptions and Speculative Execution , 1998, CAV.
[5] Gurindar S. Sohi,et al. Master/slave speculative parallelization , 2002, MICRO.
[6] Koushik Sen,et al. An Executable Specification of Asynchronous Pi-Calculus Semantics and May Testing in Maude 2.0 , 2002, Electron. Notes Theor. Comput. Sci..
[7] Tetsuo Tamai,et al. CAFE: An Industrial-Strength Algebraic Formal Method , 2000 .
[8] Leslie Lamport,et al. What Good is Temporal Logic? , 1983, IFIP Congress.
[9] Gurindar S. Sohi,et al. Multiscalar processors , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.
[10] Craig Zilles,et al. Formal Verification of MSSP , 2003 .
[11] Gurindar S. Sohi,et al. Master/slave speculative parallelization and approximate code , 2002 .
[12] Alan J. Hu,et al. Protocol verification as a hardware design aid , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.
[13] Jun Sawada,et al. Trace Table Based Approach for Pipeline Microprocessor Verification , 1997, CAV.
[14] David L. Dill,et al. Automatic verification of Pipelined Microprocessor Control , 1994, CAV.
[15] Xiaowei Shen,et al. Using term rewriting systems to design and verify processors , 1999, IEEE Micro.