Arithmetic Unit for Finite Field ${\rm GF}(2^{m})$

An arithmetic unit (AU) that performs all basic arithmetic operations in the finite field GF(2m) is presented, where m is an arbitrary integer. The presented finite field AU consists of an arithmetic processor, an arithmetic logic unit, and a control unit. The proposed AU has low circuit complexity and is programmable, so that any error-correcting decoder that operates in GF(2m) can be easily implemented with this AU.

[1]  Craig K. Rushforth,et al.  A Cellular-Array Multiplier for GF(2m) , 1971, IEEE Transactions on Computers.

[2]  Anh Dinh,et al.  A low latency architecture for computing multiplicative inverses and divisions in GF(2/sup m/) , 2000, 2000 Canadian Conference on Electrical and Computer Engineering. Conference Proceedings. Navigating to a New Era (Cat. No.00TH8492).

[3]  Wolfgang Hoeg,et al.  Digital audio broadcasting : principles and applications of digital radio , 2005 .

[4]  Soonhak Kwon,et al.  A Digit-Serial Multiplier for Finite Field , 2005 .

[5]  Trieu-Kien Truong,et al.  VLSI Architectures for Computing Multiplications and Inverses in GF(2m) , 1983, IEEE Transactions on Computers.

[6]  Shyue-Win Wei.  A Systolic Power-Sum Circuit for GF(2^m) , 1994, IEEE Trans. Computers.

[7]  Stephen B. Wicker,et al.  Reed-Solomon Codes and Their Applications , 1999 .

[8]  Chin-Liang Wang,et al.  A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2^m) , 1993, IEEE Trans. Computers.

[9]  Allen H. Levesque,et al.  Error-control techniques for digital communication , 1985 .

[10]  Shu Lin,et al.  Error control coding : fundamentals and applications , 1983 .

[11]  Zhiyuan Yan,et al.  New Systolic Architectures for Inversion and Division in GF(2^m) , 2003, IEEE Trans. Computers.

[12]  Sheng-Jyh Wang,et al.  Two systolic architectures for multiplication in GF(2m) , 2000 .

[13]  Huapeng Wu,et al.  Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis , 2002, IEEE Trans. Computers.

[14]  Chiou-Yng Lee.  Low complexity bit-parallel systolic multiplier over GF(2m) using irreducible trinomials , 2003 .

[15]  Jm Jan Smits,et al.  Digital Video Broadcasting: Technology, Standards, and Regulations , 2003 .

[16]  Stafford E. Tavares,et al.  Architectures for exponentiation in GF(2m) , 1988, IEEE J. Sel. Areas Commun..

[17]  Soonhak Kwon,et al.  A digit-serial multiplier for finite field GF(2/sup m/) , 2005, IEEE Trans. Very Large Scale Integr. Syst..

[18]  John Meyer,et al.  3G wireless with WiMAX and Wi-Fi : 802.16 and 802.11 , 2005 .

[19]  Eiji Fujiwara,et al.  Error-control coding for computer systems , 1989 .

[20]  Trieu-Kien Truong,et al.  Systolic Multipliers for Finite Fields GF(2m) , 1984, IEEE Transactions on Computers.

[21]  Dowon Hong,et al.  Low complexity bit-parallel multiplier for GF(2/sup m/) defined by all-one polynomials using redundant representation , 2005, IEEE Transactions on Computers.