A 90k Gate "CLB" for Parallel Distributed Computing

A reconfigurable architecture using distributed logic block processing elements (PEs) is presented. This distributed processor uses a low-cost interconnection network and local indirect VLIW memories to provide efficient algorithm implementations for portable battery operated products. In order to provide optimal algorithm performance, the VLIWs loaded to each PE configure that PE for processing. By reloading the local VLIW memories, each PE is reconfigured for a new algorithm. Different levels of flexibility are feasible by varying the complexity of the distributed PEs in this architecture.

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