The design of asynchronous FIFO with verilog HDL

Asynchronous FIFO(First-In First-Out)is a general way to communicate between different clock domains digital IC design.This thesis makes an analysis and research for asynchronous FIFO memory,using gray code pointers and dividing the address space into some quadrants to distinguish between full and empty.The design is based on the verilog HDL language,and the results of model sim simulation and FPGA verification both indicate the design is feasible.