RF-Interconnect Resource Assignment and Placement Algorithms in Application Specific ICs to Improve Performance and Reduce Routing Congestion

RF/wireless interconnect is an emerging technology for mitigating the problems of nano-scale metal wires in ultra-large integrated circuits. However, there is no EDA physical design flow for using this technology in conventional application specific ICs. In this paper, an architecture containing both wired and wireless interconnects is presented for regular ASICs corresponding with assignment and placement algorithms for RF-interconnect resources. Experimental results show that total wirelength (routing congestion) and critical delay of attempted benchmarks is reduced by 16.8% and 30.1% on average, respectively. These benefits are earned in the cost of 2.33% area and 11.89% power consumption overhead for large circuits. Moreover, paper concludes that the area and power consumption overheads are lower considerably when the size of design grows.

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