New sample-and-hold for high frequency applications
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Presents a novel fast and accurate sample-and-hold (S/H) circuit which can be designed using conventional low-gain amplifiers. Moreover, the offset contribution to the output voltage is intrinsically compensated for and the clock-feedthrough error can be reduced by slightly changing the clock scheme. In order to validate its performance, the proposed S/H circuit was implemented using a single-stage differential amplifier with current mirror active load and simulated with the model parameters of a standard 2-/spl mu/m CMOS process.<<ETX>>
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