A Distributed Cache Coherence Protocol for Hypercube Multiprocessors
暂无分享,去创建一个
[1] Paul Feautrier,et al. A New Solution to Coherence Problems in Multicache Systems , 1978, IEEE Transactions on Computers.
[2] Michael J. Flynn,et al. Linked list cache coherence for scalable shared memory multiprocessors , 1993, [1993] Proceedings Seventh International Parallel Processing Symposium.
[3] Andrew W. Wilson,et al. Hierarchical cache/bus architecture for shared memory multiprocessors , 1987, ISCA '87.
[4] Dharma P. Agrawal,et al. Generalized Hypercube and Hyperbus Structures for a Computer Network , 1984, IEEE Transactions on Computers.
[5] Laxmi N. Bhuyan,et al. Cache coherent shared memory hypercube multiprocessors , 1992, [1992] Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing.
[6] Laxmi N. Bhuyan,et al. Design of an Adaptive Cache Coherence Protocol for Large Scale Multiprocessors , 1992, IEEE Trans. Parallel Distributed Syst..
[7] R. Sarnath,et al. Proceedings of the International Conference on Parallel Processing , 1992 .
[8] Laxmi N. Bhuyan,et al. Design and Analysis of Cache Coherent Multistage Interconnection Networks , 1993, IEEE Trans. Computers.
[9] David J. Lilja,et al. Cache coherence in large-scale shared-memory multiprocessors: issues and comparisons , 1993, CSUR.
[10] Eugene D. Brooks. The shared memory hypercube , 1988, Parallel Comput..
[11] Corporate. IEEE Standard for Scalable Coherent Interface, Science: IEEE Std. 1596-1992 , 1993 .