Path verification using Boolean satisfiability
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[1] Alexander Saldanha,et al. Is redundancy necessary to reduce delay? , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] Robert K. Brayton,et al. Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network , 1989, 26th ACM/IEEE Design Automation Conference.
[3] Tracy Larrabee,et al. Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] David Hung-Chang Du,et al. On the General False Path Problem in Timing Analysis , 1989, 26th ACM/IEEE Design Automation Conference.
[5] Robert K. Brayton,et al. Integrating functional and temporal domains in logic design , 1991 .
[6] Sharad Malik,et al. Computation of floating mode delay in combinational circuits: theory and algorithms , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] Jacob A. Abraham,et al. VIPER: An Efficient Vigorously Sensitizable Path Extractor , 1993, 30th ACM/IEEE Design Automation Conference.
[8] J. Freeman. Improvements to propositional satisfiability search algorithms , 1995 .
[9] Hugo De Man,et al. Static Timing Analysis of Dynamically Sensitizable Paths , 1989, 26th ACM/IEEE Design Automation Conference.