A Cost-effective Fixed/floating-point Digital Signal Processor

A cost-effective fixedfloating-point digital signal processor is presented. It consists of an instruction processing unit, a 1K-byte instruction memory, a data processing unit, and four 1K-byte data memory bands. Especially, the data processing unit includes a 32-bit fixed-point arithmetic logic unit, a 16-bit fixed-point multiplier, and a simple control function. It can support fixed-point and floating-point arithmetic operations. In this design, there is no additional adders required for calculating and normalizing the exponent components of floating-point data. The floating-point or fixed-point arithmetic operations are determined by a simple control function. This provides users more flexibly to handle floating-point and fixed-point operations for the maximum throughput in a low-cost design. When considering the instruction set, there are 48 specific instructions and 16 parallel instructions which are optimized for the commonlyused operations of signal processing. As compared to the commercial digital signal processors, the proposed costeffective processor is very attractive and useful for various industrial applications. I . Introduction Various commercial hardware products of signal processing algorithms have been widely utilized in many applications. The manufactures always try to find a highperformance and low-cost solution in order to make products marketable and profitable [I-31. Currently, some of these hardware products are realized by using digital signal processors (DSPs). The DSPs are efficiently programmable processors to execute the signal processing algorithms [4-71. They are designed to have fast instruction cycle times, a high degree of parallelism, and sophisticated arithmetic units that execute in a single machine cycle. In addition, users or designers can easily obtain these commercial DSPs, such as Motorola DSP-5600/9600 and Texas Instruments TMS320C40/50, and program them for any application. In this paper, a cost-effective programmable Harvard architecture is proposed for a fixedfloating-point DSP which consists of an instruction processing unit, an instruction memory, a data processing unit, and four data memory bands. The operations of an instruction processing unit are to decode the instructions into control signals and addresses for the data processing unit and data memory bands. The data processing unit receives control signals and data from the instruction processing unit for further information processing. Here, the data processing unit includes a 32-bit fixed-point arithmetic logic unit, a 16-bit fixed-point multiplier, and a simple fixedfloating-point control function. This control function determines fixed-point or floating-point operations. At fixedpoint operations, a 32-bit arithmetic logic unit (ALU) and a 16-bit mdtiplier can be performed independently for parallel instructions. In floating-point operations, the floating-point multiplication needs a 16-bit multiplier for the mantissa computing and a half of the 32-bit ALU for the exponent computing. The floating-point addition only requires a 32-bit ALU for the computation of mantissa and exponent components. In the instruction set, the 64 instructions with pipelined operations are utilized to support the signal processing. There are 4 addressing modes of immediate, direct, indirect, and circular. The proposed processor can have much simple decoding of instructions and optimized bandwidths of control units as compared to the commercial DSPs having a hundred of instructions. The pipelined operations of an instruction include fetching, decoding, reading and executing at four clock cycles [SI. The operations of neighboring instructions can be overlapped with three clock cycles such that each instruction can be carried out in one clock cycle for highspeed information processing. 2. Arithmetic Operations of DSPs Digital signal processors are often characterized by the signal processing algorithms. These algorithms specify the computation of arithmetic operations but does not specify their implementation. In general, arithmetic operations such as addition and multiplication are the major operations of signal processing algorithms. As a result, numerical formats of arithmetic operations can have an essential impact on the performance of the signal processing system. Hence, the most important choice for a designer is among fixed-point and floating-point arithmetic operations. Before to realize the signal processing algorithms, we need to understand how the DSP hardware affect precision and range [9]. Floating-point arithmetic operations provide much greater dynamic ranges than fixed-point arithmetic operations. They can considerably simplify the algorithm and software design due to reducing the probability of overflow and the necessity of scaling. Unfortunately, floating-point arithmetic operations are more expensive in numerical computation, and more complicated in hardware implementation than fixed-point arithmetic operations.