Symbolic optimization of interacting controllers based onredundancy identification and removal
暂无分享,去创建一个
[1] Robert K. Brayton,et al. The maximum set of permissible behaviors for FSM networks , 1993, ICCAD.
[2] David Bryan,et al. Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.
[3] Robert K. Brayton,et al. Permissible Observability Relations in FSM Networks , 1994, 31st Design Automation Conference.
[4] Kwang-Ting Cheng. On removing redundancy in sequential circuits , 1991, 28th ACM/IEEE Design Automation Conference.
[5] Robert K. Brayton,et al. Sequential circuit design using synthesis and optimization , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.
[6] Robert K. Brayton,et al. Input don't care sequences in FSM networks , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[7] Stephen H. Unger,et al. Asynchronous sequential switching circuits , 1969 .
[8] Dana S. Scott,et al. Finite Automata and Their Decision Problems , 1959, IBM J. Res. Dev..
[9] Fabrizio Ferrandi,et al. VHDL testability analysis based on fault clustering and implicit fault injection , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).
[10] Bill Lin,et al. Modeling and optimization of hierarchical synchronous circuits , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.
[11] T. Villa,et al. Implicit state minimization of non-deterministic FSMs , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.
[12] Fabio Somenzi,et al. Don't care sequences and the optimization of interacting finite state machines , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[13] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[14] Jeffrey D. Ullman,et al. Formal languages and their relation to automata , 1969, Addison-Wesley series in computer science and information processing.
[15] Robert K. Brayton,et al. Input don't care sequences in FSM networks , 1993, ICCAD '93.
[16] S. Yang,et al. Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .
[17] Monty Newborn,et al. The Simplification of Sequential Machines with Input Restrictions , 1972, IEEE Transactions on Computers.
[18] Robert K. Brayton,et al. State minimization of pseudo non-deterministic FSMs , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.
[19] Srinivas Devadas. Optimizing interacting finite state machines using sequential don't cares , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[20] Fabio Somenzi,et al. Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[21] Kwang-Ting Cheng,et al. Sequential logic optimization by redundancy addition and removal , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[22] Alberto L. Sangiovanni-Vincentelli,et al. Irredundant sequential machines via optimal logic synthesis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[23] Maurizio Damiani. Nondeterministic finite-state machines and sequential don't cares , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.