Trellis-Based Extended Min-Sum Algorithm for Non-Binary LDPC Codes and its Hardware Structure
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[1] David Declercq,et al. Decoding Algorithms for Nonbinary LDPC Codes Over GF$(q)$ , 2007, IEEE Transactions on Communications.
[2] Jianhao Hu,et al. FPGA implementation of nonbinary quasi-cyclic LDPC decoder based on EMS algorithm , 2009, 2009 International Conference on Communications, Circuits and Systems.
[3] Ajay Dholakia,et al. Efficient implementations of the sum-product algorithm for decoding LDPC codes , 2001, GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).
[4] Gwan S. Choi,et al. A Parallel VLSI Architecture for Layered Decoding , .
[5] Xinmiao Zhang,et al. Partial-parallel decoder architecture for quasi-cyclic non-binary LDPC codes , 2010, 2010 IEEE International Conference on Acoustics, Speech and Signal Processing.
[6] Valentin Savin,et al. Min-Max decoding for non binary LDPC codes , 2008, 2008 IEEE International Symposium on Information Theory.
[7] David Declercq,et al. Design of regular (2,d/sub c/)-LDPC codes over GF(q) using their binary images , 2008, IEEE Transactions on Communications.
[8] Mohammed Atiquzzaman,et al. VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax , 2007, 2007 IEEE International Conference on Communications.
[9] Fang Cai,et al. Architecture for Non-binary LDPC Decoding , 2011 .
[10] Henk Wymeersch,et al. Log-domain decoding of LDPC codes over GF(q) , 2004, 2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577).
[11] David Declercq,et al. Low-complexity decoding for non-binary LDPC codes in high order fields , 2010, IEEE Transactions on Communications.
[12] Luca Gaetano Amarù,et al. High Speed Architectures for Finding the First two Maximum/Minimum Values , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[13] Shu Lin,et al. Construction of Quasi-Cyclic LDPC Codes for AWGN and Binary Erasure Channels: A Finite Field Approach , 2007, IEEE Transactions on Information Theory.
[14] Xiaoheng Chen,et al. High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.
[15] D.J.C. MacKay,et al. Good error-correcting codes based on very sparse matrices , 1997, Proceedings of IEEE International Symposium on Information Theory.
[16] Emmanuel Boutillon,et al. Bubble check: a simplified algorithm for elementary check node processing in extended min-sum non-binary LDPC decoders , 2010 .
[17] C. Spagnol,et al. Hardware Implementation of LDPC Decoders , 2009 .
[18] Robert G. Gallager,et al. Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.
[19] Zhongfeng Wang,et al. Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.
[20] David Declercq,et al. Trellis based Extended Min-Sum for decoding nonbinary LDPC codes , 2011, 2011 8th International Symposium on Wireless Communication Systems.
[21] Enrico Paolini,et al. Low-Density Parity-Check (LDPC) Codes , 2013 .
[22] Zongwang Li,et al. A Simplified Min-Sum Decoding Algorithm for Non-Binary LDPC Codes , 2012, IEEE Transactions on Communications.
[23] C. Spagnol,et al. Hardware Implementation of ${\rm GF}(2^{m})$ LDPC Decoders , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.
[24] Robert Michael Tanner,et al. A recursive approach to low complexity codes , 1981, IEEE Trans. Inf. Theory.
[25] D. Mackay,et al. Low density parity check codes over GF(q) , 1998, 1998 Information Theory Workshop (Cat. No.98EX131).
[26] David Declercq,et al. Non-binary coding for vector channels , 2011, 2011 IEEE 12th International Workshop on Signal Processing Advances in Wireless Communications.
[27] R. M. Tanner,et al. A Class of Group-Structured LDPC Codes , 2001 .
[28] Haiqiang Chen,et al. Low Complexity X-EMS Algorithms for Nonbinary LDPC Codes , 2012, IEEE Transactions on Communications.
[29] X. Jin. Factor graphs and the Sum-Product Algorithm , 2002 .