A 200 MHz quadrature digital synthesizer/mixer in 0.8 /spl mu/m CMOS
暂无分享,去创建一个
[1] Andrew D. Booth,et al. A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .
[2] H. Samueli,et al. The optimization of direct digital frequency synthesizer performance in the presence of finite word length effects , 1988, Proceedings of the 42nd Annual Frequency Control Symposium, 1988..
[3] H. Samueli,et al. A 200-MHz all-digital QAM modulator and demodulator in 1.2- mu m CMOS for digital radio applications , 1991 .
[4] Jack Sklansky,et al. Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..
[5] H. Samueli,et al. An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Presence of Phase-Accumulator Truncation , 1987, 41st Annual Symposium on Frequency Control.
[6] M. Thompson. Low-latency, high-speed numerically controlled oscillator using progression-of-states technique , 1992 .
[7] B. Gold,et al. A digital frequency synthesizer , 1971 .
[8] H. Samueli,et al. A 150-MHz Direct Digital Frequency Synthesizer In 1.25/spl mu/m CMOS With -90dBc Spurious Performance , 1991 .
[9] Christer Svensson,et al. High-speed CMOS circuit technique , 1989 .