Building and using a highly parallel programmable logic array

A two-slot addition called Splash, which enables a Sun workstation to outperform a Cray-2 on certain applications, is discussed. Following an overview of the Splash design and programming, hardware development is described. The development of the logic description generator is examined in detail. Splash's runtime environment is described, and an example application, that of sequence comparison, is given.<<ETX>>

[1]  H. T. Kung Why systolic architectures? , 1982, Computer.

[2]  H. T. Kung,et al.  The Warp Computer: Architecture, Implementation, and Performance , 1987, IEEE Transactions on Computers.

[3]  Daniel P. Lopresti,et al.  P-NAC: A Systolic Array for Comparing Nucleic Acid Sequences , 1987, Computer.

[4]  Shekhar Y. Borkar,et al.  iWarp: an integrated solution to high-speed parallel computing , 1988, Proceedings. SUPERCOMPUTING '88.

[5]  Zvi M. Kedem,et al.  On high-speed computing with a programmable linear array , 1988, Supercomputing '88.

[6]  Daniel J. Kopetzky HORSE: a simulation of the Horizon supercomputer , 1988, Proceedings. SUPERCOMPUTING '88.

[7]  Jean Vuillemin,et al.  Introduction to programmable active memories , 1990 .

[8]  Daniel P. Lopresti,et al.  SPLASH: A Reconfigurable Linear Logic Array , 1990, ICPP.

[9]  Ronald G. Minnich,et al.  The Logic Description Generator , 1990, [1990] Proceedings of the International Conference on Application Specific Array Processors.