A Semantic Association Hardware Acceleration System for Integrated Product Data Management

Many modern products are complex systems comprised of highly integrated mechanical, electrical, electronic, and software components, which are commonly known as mechatronic systems. Similarly, product data and life-cycle management systems that support the engineering and design of mechatronic systems are becoming complex and need to store, retrieve, and process vast amounts of files associated with mechatronic products. For many years, software developers and computer architects have benefited by continuous increases in computational performance, as predicted by Moore’s law. However, issues such as extreme power consumption have begun to limit certain types of performance increases such as hardware clock rates. In an effort to find new ways to increase computational performance, engineers and computer scientists have been investigating new techniques such as hardware acceleration systems, reconfigurable computing, and heterogeneous computing (HC). In light of these emerging computational paradigms, this paper introduces a semantic association hardware acceleration system for integrated product data management (PDM) based on semantic file systems. The concept of semantic path merger (SPM) is described along with a discussion of its realization as a hardware-based associative memory for accelerated semantic file retrieval. The energy and retrieval performance metrics of the proposed hardware system is given along with its comparative analysis with the industry standard content addressable memory (CAM). The goal of the proposed system is to enhance the state-of-art for the field of heterogeneous computing within the scope of computational platforms for design and engineering applications.

[1]  Norman P. Jouppi,et al.  WRL Research Report 93/5: An Enhanced Access and Cycle Time Model for On-chip Caches , 1994 .

[2]  Jitesh H. Panchal,et al.  A Framework for The Integrated Design of Mechatronic Products , 2009 .

[3]  Dennis M. Buede,et al.  The Engineering Design of Systems: Models and Methods , 1999 .

[4]  T. N. Vijaykumar,et al.  Dynamic pipelining: making IP-lookup truly scalable , 2005, SIGCOMM '05.

[5]  Ying Liu,et al.  Faceted search and retrieval based on semantically annotated product family ontology , 2009, ESAIR '09.

[6]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[7]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[8]  Peter A. Fritzson,et al.  Principles of object-oriented modeling and simulation with Modelica 2.1 , 2004 .

[9]  Scott Hauck,et al.  Reconfigurable computing: a survey of systems and software , 2002, CSUR.

[10]  John F. Sowa,et al.  Conceptual Structures: Information Processing in Mind and Machine , 1983 .

[11]  Norman P. Jouppi,et al.  CACTI 2.0: An Integrated Cache Timing and Power Model , 2002 .

[12]  K. Pagiamtzis,et al.  Content-addressable memory (CAM) circuits and architectures: a tutorial and survey , 2006, IEEE Journal of Solid-State Circuits.

[13]  Christiaan J. J. Paredis,et al.  Enabling Multi-View Modeling with SysML Profiles and Model Transformations , 2009 .

[14]  Victor Raskin,et al.  DEVELOPING ONTOLOGIES FOR ENGINEERING INFORMATION RETRIEVAL , 2007 .

[15]  Wilson C. Hsieh,et al.  Bigtable: A Distributed Storage System for Structured Data , 2006, TOCS.

[16]  Norman P. Jouppi,et al.  CACTI 6.0: A Tool to Model Large Caches , 2009 .

[17]  Viktor K. Prasanna,et al.  A Memory-Balanced Linear Pipeline Architecture for Trie-based IP Lookup , 2007 .

[18]  John Shalf,et al.  The new landscape of parallel computer architecture , 2007 .

[19]  P.P. Gelsinger,et al.  Microprocessors for the new millennium: Challenges, opportunities, and new frontiers , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[20]  Andrew B. Kahng,et al.  ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[21]  Viktor K. Prasanna,et al.  Sequence-preserving parallel IP lookup using multiple SRAM-based pipelines , 2009, J. Parallel Distributed Comput..

[22]  Sartaj Sahni,et al.  Efficient Construction of Pipelined Multibit-Trie Router-Tables , 2007, IEEE Transactions on Computers.

[23]  Leonid Oliker,et al.  Reconfigurable hybrid interconnection for static and dynamic scientific applications , 2007, CF '07.

[24]  Sharad Malik,et al.  Orion: a power-performance simulator for interconnection networks , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

[25]  Dirk Schaefer,et al.  A semantic file system for integrated product data management , 2011, Adv. Eng. Informatics.

[26]  Xin He,et al.  LOP: a novel SRAM-based architecture for low power and high throughput packet classification , 2009, CODES+ISSS '09.

[27]  Wai Ming Cheung,et al.  Product lifecycle management: state-of-the-art and future perspectives , 2010 .

[28]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[29]  Quyet-Thang Le,et al.  Towards Ontology-based Semantic File Systems , 2007, 2007 IEEE International Conference on Research, Innovation and Vision for the Future.

[30]  George Bourianoff,et al.  Emerging Nanoscale Memory and Logic Devices: A Critical Assessment , 2008, Computer.

[31]  Rolf Riesen,et al.  A framework for architecture-level power, area, and thermal simulation and its application to network-on-chip design exploration , 2011, PERV.

[32]  Norman P. Jouppi,et al.  Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0 , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[33]  Xin He,et al.  LOP_RE: Range encoding for low power packet classification , 2009, 2009 IEEE 34th Conference on Local Computer Networks.

[34]  Girija J. Narlikar,et al.  Fast incremental updates for pipelined forwarding engines , 2005, IEEE/ACM Transactions on Networking.