A circuit-level perspective of the optimum gate oxide thickness

A performance constrained minimum power-area optimization is introduced to project the physical gate oxide thickness (t/sub ox/) scaling limit from a circuit-level perspective. The circuit optimization is based on the recent physical alpha-power law MOSFET model that enables predictions of CMOS circuit performance for future generations of technology. The model is utilized to derive an equation for propagation delay including the transition time effect. A physical compact gate-tunneling current model is also derived to analyze ultrathin oxide layers. Results indicate that the gate-tunneling power is substantially less (<5%) than the drain-to-source leakage power at the oxide thickness required for optimum CMOS logic circuit performance. As t/sub ox/ is scaled below 3.0 nm, the MOSFET performance improvement resulting from t/sub ox/ scaling diminishes due to an increasing effect of the polysilicon gate depletion depth on the electrical effective oxide thickness. The gate-tunneling power, however, remains exponentially dependent on t/sub ox/, thus resulting in an optimal value of t/sub ox/ where the gate-tunneling power is negligible in comparison to the drain-to-source leakage power. The scaling limit of t/sub ox/ is projected as 2.2, 1.9, and 1.4 nm for the 180, 150, and 100 nm technology generations, respectively.