Implementation of Digital Pulse Compression System Based on FPGA

A single-channel high-speed data acquisition and digital pulse compression system is implemented for the wideband radar system with LFM signal.ADS5500 is used for 14 b,60MSPS data acquisition and FPGA is used for 1024 points digital pulse compression(DPC).The DPC module is designed using FFT IP core which can be reused in different periods of DPC,respectively performing FFT and IFFT calculation,so that the hardware consumption is saved significantly.The block floating-point data format is used to enhance dynamic range,and diminish truncation or rounding error which affects the output signal to noise ratio.